Hardware Reference
In-Depth Information
valid) that is asserted during one clock cycle to inform that the data is ready (to be
stored, processed, etc.). In many cases the i rst data bit (or vector) is made available
at the same time that
dv
is asserted, so one must be very careful not to miss that i rst
bit (or vector).
An example is shown in i gure 3.16a, which consists of a serial data receiver. The
FSM must store the input data
x
in a register
y
. Note that it is a timed machine, which
must stay in state B during
T
clock cycles, where
T
is the number of bits of
x
to be
stored in
y
. This i rst solution is of Moore type and employs the default clocking
scheme (everybody clocked at the same clock edge—positive by default—as indicated
in the rectangle in the upper part of the i gure).
An illustrative timing diagram for the FSM of i gure 3.16a is presented in i gure
3.16b, for
x
= “1011” (see the shaded area on the
x
waveform). The problem with this
solution is that it misses the i rst bit of
x
because the machine only moves to state B
at the i rst (positive) clock edge after
dv
= '1' occurs (note in the i gure that when the
Figure 3.16
Techniques for capturing the i rst bit when it coincides with
dv
. (a, b) Bad Moore solution. (c, d)
Fine Moore solution. (e, f) Fine Mealy solution.
