Hardware Reference
In-Depth Information
Figure 3.15
A simple solution for truly safe state machines when using sequential encoding.
the column q 1 q 0 = “11” is the critical column because all elements in that column can
be i lled indifferently with '0' or '1', so a number of different equations can be used
for d 1 and d 0 . We have to make certain that the condition nx_state = pr_state (i.e., d 1 d 0
= q 1 q 0 ) never happens, either directly or through a loop in the external states, because
then deadlock will occur.
The maps of i gure 3.14c were repeated in i gures 3.14d-f for three different com-
positions of the critical columns. In i gure 3.14d, all positions were i lled with '1's, so
d 1 d 0 = “11” results when q 1 q 0 = “11” (i.e., nx_state = pr_state ) for both x = '0' (upper
row) and x = '1' (lower row), causing deadlock. In i gure 3.14e, d 1 d 0 = “11” for x = '0'
(upper row) and d 1 d 0 = “10” for x = '1' (lower row), so a deadlock would occur in the
former, and a convergence to state A3 would occur in the latter. Finally, the case in
i gure 3.14f has d 1 d 0 = “00” for x = '0' and d 1 d 0 = “10” for x = '1', so both would con-
verge (to A1 and A3, respectively).
Figure 3.14g shows the complete resulting state diagram (internal plus external
states) in case the encoding of i gure 3.14f is adopted. As seen above, B converges to
A1 if x = '0' or to A3 if x = '1', so this is a truly safe implementation.
To conclude, the Karnaugh maps are repeated in i gure 3.14h, in which the optimal
(minimal) expressions were adopted for nx_state (i.e., d 1 and d 0 ). Note that the result-
ing situation is that of i gure 3.14e, subject, therefore, to deadlock. In summary, in
this example the optimal implementation from a hardware-saving perspective is not
the best implementation from a safety point of view.
We conclude this section by showing, in i gure 3.15, a simple solution that is appli-
cable to FSMs that employ sequential encoding. M is the machine's number of states.
If M = 20, for example, i ve bits are needed, and the state values will range from 0 to
19. If at any moment (either at initialization or during regular operation) pr_state
happens to be above 19, it means that an external state has occurred, so a reset pulse
is produced (this reset can be combined with the original reset signal, if it exists, by
means of an OR gate). The l ip-l op in i gure 3.15 is needed because the comparator
can have glitches at the output during state transitions (see, for example, i gure 2.15).
3.10 Capturing the First Bit
This section discusses a common hardware need that occurs, for example, when data
is processed serially. In such cases there is often an input bit (here called dv , for data
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