Hardware Reference
In-Depth Information
Figure 2.6
Illustration of l ip-l op metastability and the use of synchronizers.
Figure 2.7
Partial diagram for a frequency meter (two clock domains). (a) Solution with a Gray counter. (b)
Solution with a synchronizer (so a regular counter can be employed).
though it might be different from the expected value); otherwise, an undetermined
value will be read.
Synchronizers are circuits used to cope with metastability. The most common alter-
native is shown in i gure 2.6b, consisting simply of a 2-stage shift register. In well-
designed DFFs the probability of metastability is very small so the probability of having
such a rare event going through both DFFs is extremely small. The obvious drawback
is the two-clock-period latency imposed by this circuit (exercise 2.2). When the (multi-
bit) data is accompanied by a control signal (data ready, i gure 2.6c), only the control
signal should be synchronized.
Another strategy to reduce the impact of having the input of a DFF change during
its forbidden time window, applicable to counters, consists in using Gray counters
instead of regular sequential counters (as reviewed in section 3.7, in a Gray counter
only one bit changes from one codeword to the next—this applies also to Johnson
counters). An example is depicted in i gure 2.7a, which shows a partial diagram for
a frequency meter. Because the system must measure the frequency
fx
of
x
,
x
acts
as the clock to the corresponding counter; however,
x
and
clk
are uncorrelated, so a
two-clock-domain situation results. The value of
fx
must be stored into the output
