Hardware Reference
In-Depth Information
register periodically (every 1 s, for example, resulting in a reading in Hz), and at the
same time the counter must be reset in order to start a new counting. Because
x
and
clk
are uncorrelated, the storage of
fx
into the register might occur while
fx
is changing
its value. If a sequential counter is used, several bits (or even all) can change from one
codeword to the next, but because in a Gray counter only one bit changes, the value
actually stored into the register cannot be off by more than one unit.
For comparison, a solution with a synchronizer (so a regular counter can be used)
is included in i gure 2.7b. Note that the synchronizer's output must be a short pulse
(lasting only one clock period,
T
clk
); otherwise the counter could be incremented mul-
tiple times for the same pulse of
x
. Additionally, if a pulse in
x
might last less than
T
clk
, then an edge detector must also be included. (One-shot and edge-detecting circuits
are described in the next section.)
A last class of circuits still involving the synchronous-asynchronous issue is pre-
sented in i gure 2.8. They are
clock gaters
, needed in applications where the clock signal
must be stopped (gated) during one or more clock periods (the I
2
C and SPI serial data
communications interfaces, studied in chapter 14, are examples where clock gating is
necessary). The purpose here should not be confused with clock gating for power-
saving reasons.
Figures 2.8a-f relate to
positive
-edge-triggered FSMs. Figure 2.8a highlights the facts
that the machine operates at the positive clock edge and also that the clock-enabling
signal
ena
is just one of its outputs. This signal (
ena
) must stop the clock when low,
replacing the clock signal with a static-low value (analogous solutions can be easily
derived for a static-high value).
The i rst solution, shown in i gure 2.8b, is asynchronous and requires just an AND
gate, where
clk
represents the main clock and
gclk
represents its gated version. The
advantage of this solution is that the clock is interrupted at the same time that
ena
=
'0' occurs (see gray shades in i gures 2.8c-d). However, as depicted in the timing dia-
grams of i gures 2.8c-d, the output is i ne (glitch-free) only if the edge of
ena
reaches
the gater
before
the edge of
clk
does, a situation that, though possible (due to long,
unbalanced routings inside the chip), is very unlikely. Moreover, glitches in
ena
can
propagate to the output. For these reasons, the clock gater of i gure 2.8b is not recom-
mended when the clock must be replaced with a static-low value.
The second solution, shown in i gure 2.8e, is fully synchronous, so occasional
glitches in
ena
are automatically i ltered out. Also, note in i gure 2.8f that the output
is i ne regardless of the delay (positive or negative) between
clk
and
ena
. For these
reasons, the clock gater of i gure 2.8e is recommended when the clock must be inter-
rupted and replaced with a zero. Its drawback is that now
ena
= '0' must be produced
in the
previous
clock cycle (previous FSM state—see gray shades in i gure 2.8f), being
therefore more error prone (requiring greater attention when preparing the corre-
sponding state transition diagram).
