Hardware Reference
In-Depth Information
Figure 2.5
Examples of actual DFF constructions. (a, b) Very popular implementations (dynamic and static
versions, master-slave approach). (c, d) Two other commercial implementations (pulsed-latch
approach).
input signal must remain stable. If
d
changes within the transparency window, the
output value might be undetermined (further details on this are seen in the next
section).
We conclude this section by presenting some examples of DFF constructions. The
cases in i gures 2.5a,b are among the most commonly used, consisting of dynamic
and static versions for the same transmission-gate-based master-slave implementation.
Two other commercial cases are shown in i gures 2.5c,d, both based on the short-clock
(pulsed latch) principle rather than on the master-slave approach.
2.3 Metastability and Synchronizers
Because many FSMs have control inputs that are asynchronous (that is, not related to
the FSM's clock), such inputs can change during the state machine's DFFs' forbidden
(aperture) window. This section describes what can happen in such cases and how its
effect can be reduced.
This fact is illustrated in i gure 2.6a, in which
d
changes precisely within the forbid-
den time interval (gray area). When this occurs, the output can go into an undeter-
mined (metastable) state that lasts a relatively long time before i nally resolving for
'1' (path 1) or '0' (path 2). If the metastable state resolves within one clock period (as
in the i gure), at the next (positive) clock edge a valid value will be available (even
