Hardware Reference
In-Depth Information
Figure 2.1
Symbol and truth table for basic (a) positive-edge and (b) negative-edge DFFs.
Figure 2.2
DFF symbol with (a) reset or (b) clear, followed by examples of
functional
response. (c) Diagram
showing how clear can be implemented.
under any other condition. For this reason, it is said that a positive-edge-triggered (or
simply positive-edge) DFF is “transparent” during positive clock transitions and
“opaque” elsewhere.
Figure 2.1b shows the symbol and truth table for a basic negative-edge-triggered
(or simply negative-edge) DFF (note the little circle at the clock input). This DFF is
“transparent” during negative clock transitions (see last table line) and “opaque”
elsewhere.
The behavior of any digital circuit can be expressed by means of its
functional
and
timing
responses. The former takes into account only the circuit's logical functions,
thus conveying only its functional behavior, whereas the latter also takes into account
the propagation delays as the signals travel through the circuit, thus expressing the
circuit's actual behavior. Both types of responses (functional and timing) are illustrated
next for l ip-l ops.
Figure 2.2 shows (on the left) two DFFs, the i rst having a reset (
rst
) input, and the
second a clear (
clr
) input. In the context of this topic the difference between reset and
clear is that the former is asynchronous (it forces the output to zero regardless the
clock value), whereas the latter is synchronous (the output is forced to zero when the
proper clock transition occurs). It is important to mention, however, that these des-
