Hardware Reference
In-Depth Information
2 Hardware Fundamentals—Part I
2.1 Introduction
This chapter and the one that follows discuss fundamental hardware-related aspects
and introduce new material essential to fully understand and correctly design i nite
state machines in hardware. This chapter deals mainly with registers, and the next
deals with the complete state machine structure.
The topics seen in these two chapters are used, reinforced, and expanded as the
subsequent chapters unfold, particularly in chapters 5 (theory for category 1 machines),
8 (theory for category 2 machines), and 11 (theory for category 3 machines).
2.2 Flip-Flops
Flip-l ops are available in four versions: SR (set-reset), D (data), T (toggle), and JK. The
D-type l ip-l op (DFF) is a general-purpose l ip-l op and therefore the most commonly
used. However, because counters are among the most common digital circuits, and
counters are implemented with T-type l ip-l ops (TFFs), the TFF is also very popular.
Nevertheless, because a TFF can be obtained from a DFF by simply connecting an
inverted version of its output back to its input, the DFF is essentially the only l ip-l op
needed in most designs, no matter how big or how complex. For instance, the DFF is
the only l ip-l op fabricated in i eld programmable gate array (FPGA) devices.
The DFF is the l ip-l op used to build the
state register
(that is, the memory that
stores the machine's state) in hardware-implemented i nite state machines (see i gure
1.2). It is also the l ip-l op used to build any other additional (optional or compulsory)
register that the machine might require. Consequently, it is important to review its
operation well.
Figure 2.1a shows the symbol and truth table for a basic positive-edge-triggered
DFF. The inputs are
d
(data in) and
clk
(clock), while the output is
q
(data out). As can
be seen in the truth table,
q
+ (which represents the next value of
q
) receives the value
of
d
when a positive clock transition occurs (gray table line) but remains unchanged
