Hardware Reference
In-Depth Information
Figure 15.1
(a) Single-loop FSM with a timed state and (b) LUT containing its output values.
A VHDL code for the machine of i gure 15.1 is presented below. The code contains
just one process, which builds the pointer (called
i
, lines 19-27) and the LUT (for
y
,
lines 30-36).
Note:
To save space, only VHDL codes are shown in this chapter. However, based
on these VHDL codes and on the SystemVerilog codes seen in chapters 7, 10, and 13,
writing the SystemVerilog codes for the examples described here is straightforward.
1 ------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 ------------------------------------------------
5 entity simple_machine is
6 port (
7 run, clk, rst: in std_logic;
8 y: out std_logic_vector(2 downto 0));
9 end entity;
10 ------------------------------------------------
11 architecture pointer_based of simple_machine is
12 begin
13
14
process (clk, rst)
15
variable i: natural range 0 to 9;
16
begin
17
18
--Pointer (i):
19
if (rst='1') then
20
i:= 0;
21
elsif rising_edge(clk) then
22
if (i=0 and run='0') or i=9 then
23
i:= 0;
24
else
25
i:= i + 1;
26
end if;
27
end if;
28
29
--LUT (for y):
30
case i is
31
when 0 => y <= "000";
32
when 1 => y <= "001";
33
when 2 => y <= "011";
34
when 3 to 8 => y <= "111";
