Hardware Reference
In-Depth Information
Figure 14.17
Examples of SPI behavior for (a) writing and (b) reading (FM25L512 FRAM device).
The general communication procedure consists of a number of opcodes transmitted
by the master to the slave, followed by a data-write or data-read procedure with any
number of data bytes. The only particularity is that each opcode must be preceded by
a deselect-reselect sequence.
As an example, the FRAM memory used in the design example presented ahead
requires two opcodes, called WREN (sets the write enable latch) and WRITE (enables
writing to the memory—at the next positive clock edge), before actual data writing
takes place. The same device requires one opcode, called READ (enables reading from
the memory—at the next negative clock edge), before actual data reading occurs.
Consequently, a typical l ow for the SPI interface for this FRAM is that depicted in
i gure 14.17. Note in i gure 14.17a that the device is deselected-reselected between two
consecutive opcodes. Dashed lines indicate “don't care” or high-impedance values for
the MOSI/MISO wires. Observe the safe distance between the high-to-low transitions
of
SSn
and the next positive edge of
SCK
, as well as between the low-to-high transi-
tions of
SSn
and the previous negative edge of
SCK
, both required to be at least 10 ns
in this particular device.
14.3.3 Complete Design Example: FRAM (Ferroelectric RAM) Interface
To illustrate the use of SPI, the FM25L512 FRAM mentioned above, from Ramtron, is
used as an example. It is a 64k
8 bits nonvolatile memory with serial access through
an SPI bus. Its pinout, list of opcodes, and contents of the status register are shown
in i gure 14.18. An important feature of this technology (FRAM) is that data can be
written into it at high speed (20 MHz in the present example), contrasting with
EEPROM, which generally takes a few milliseconds/page.
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