Hardware Reference
In-Depth Information
Figure 14.16
(a, b) Main SPI operating modes. (c) Slave's registers operation.
SPI is simpler than I
2
C because there is no bidirectional line, and the device selec-
tion is made with a separate wire for each slave rather than with a transmitted address.
On the other hand, SPI demands more I/O pins, can operate with only one master,
has no message acknowledgment, and because there is no standard message, format
validation would be more difi cult. SPI is said to be a four-wire bus, but that is indeed
the
least
number of wires, whereas I
2
C is truly two wires. In some cases a bidirectional
line can be used for
MOSI
and
MISO
together, resulting then a three-wire bus.
14.3.2 SPI Bus Operation
There are four SPI operating modes, determined by the clock phase (
CPHA
) and clock
polarity (
CPOL
). They are called
mode 0
(
CPHA
= 0,
CPOL
= 0),
mode 1
(
CPHA
= 0,
CPOL
= 1),
mode 2
(
CPHA
= 1,
CPOL
= 0), and
mode 3
(
CPHA
= 1,
CPOL
= 1). The two
most common modes are 0 and 3, illustrated in i gures 14.16a,b; note that in mode
0
SSn
is lowered with
SCK
low, whereas the opposite occurs in mode 3.
Figure 14.16c shows how the slave operates. It stores the data available on the MOSI
wire at positive clock edges and places data on the MISO wire at negative clock transi-
tions. Consequently, the FSM used to implement the master side of this interface must
operate at the negative clock edge, so the data provided by the machine will be ready
for the slave at the positive clock edge. Likewise, a register that records the data issued
by the slave must operate at the positive clock edge, so the data (issued at the negative
clock edge) will be ready for storage.
Part of the communication between master and slave is ruled by information stored
in eight-bit registers at both ends. These registers are not standardized, neither in
number nor in content. For example, the SPI in the Motorola MC68HC908GT micro-
controller contains three registers (for status, called SPSCR, control, SPCR, and data,
SPDR), whereas the SPI in the Maxim DS1306 RTC has two registers (for status and
control), and the SPI in the Ramtron FM25L512 FRAM memory contains only one (for
status).
