Hardware Reference
In-Depth Information
246
min(8-i) <= SDA;
247
elsif (pr_state=rd_hour) then
248
hour(8-i) <= SDA;
249
end if;
250
end if;
251
end process;
252
ssd_1sec <= bcd_to_ssd(sec(3 downto 0));
253
ssd_10sec <= bcd_to_ssd(sec(7 downto 4));
254
ssd_1min <= bcd_to_ssd(min(3 downto 0));
255
ssd_10min <= bcd_to_ssd(min(7 downto 4));
256
ssd_1hour <= bcd_to_ssd(hour(3 downto 0));
257
ssd_10hour <= bcd_to_ssd(“00” & hour(5 DOWNTO 4));
258
259 end architecture;
260 -------------------------------------------------------------------------
14.3 SPI Interface
Serial peripheral interface (SPI) is another synchronous serial bus for communication
between integrated circuits (installed next to each other, normally on the same board).
Like I
2
C, it operates in a master-slave architecture, but it is simpler to implement and
can operate at higher speeds (up to around 100 Mbps), although it requires more
interconnecting wires. Developed by Motorola for its 68HC family of microcontrollers,
it is now in widespread use.
14.3.1 SPI Bus Structure
The SPI bus general structure is depicted in i gure 14.15. In i gure 14.15a, a single slave
is shown (normally, the master is a microcontroller), so four wires are needed, called
SCK
(serial clock, always generated by the master),
MOSI
(Master Out Slave In),
MISO
(Master In Slave Out), and
SSn
(Slave Select, active low). When
SSn
is low, the slave is
selected, to/from which the master sends/receives messages through the
MOSI
/
MISO
wires. In i gure 14.15b, a multislave system is depicted, so multiple
SSn
wires are
needed. Examples of ICs with SPI support are also shown in the i gure, which are
essentially the same categories as for I
2
C (e.g., microcontrollers, EEPROM and Flash
memories, A/D and D/A converters, RTCs, and accelerometers).
Figure 14.15
General SPI bus structure with (a) single and (b) multiple slaves.
