Hardware Reference
In-Depth Information
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3.
The reader is invited to set up this (or an equivalent) experiment and play with it
in the FPGA board.
1 ----Package with function “bcd_to_ssd”:-----------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 package my_functions is
5 function bcd_to_ssd(input:std_logic_vector)
6 return std_logic_vector;
7 end my_functions;
8 --------------------------------------------------------
9 package body my_functions is
10 function bcd_to_ssd(input: std_logic_vector)
11 return std_logic_vector is
12 begin
13 case input is
14 when "0000" => return "0000001"; --"0" on SSD
15 when "0001" => return "1001111"; --"1" on SSD
16 when "0010" => return "0010010"; --"2" on SSD
17 when "0011" => return "0000110"; --"3" on SSD
18 when "0100" => return "1001100"; --"4" on SSD
19 when "0101" => return "0100100"; --"5" on SSD
20 when "0110" => return "0100000"; --"6" on SSD
21 when "0111" => return "0001111"; --"7" on SSD
22 when "1000" => return "0000000"; --"8" on SSD
23 when "1001" => return "0000100"; --"9" on SSD
24 when others => return "1111110"; --"-" on SSD
25 end case;
26 end bcd_to_ssd;
27 end package body;
28 --------------------------------------------------------
1 ----Maincode:-----------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 use work.my_functions.all; --package with “bcd_to_ssd” function
5 -------------------------------------------------------------------------
6 entity RTC_with_I2C_bus is
7
generic (
8
--Clock parameters:
9
fclk: positive := 50_000_000; --Clock frequency in Hz
10
data_rate: positive := 100_000; --Desired I2C bus speed in bps
11
--RTC addresses:
12
slave_addr_for_wr: std_logic_vector(7 downto 0) := "10100010";
13
slave_addr_for_rd: std_logic_vector(7 downto 0) := "10100011";
14
initial_addr_for_wr:std_logic_vector(7downto0):="00000000";
15
initial_addr_for_rd:std_logic_vector(7downto0):="00000010";
16
--Values to store in the RTC clock/calendar registers:
17
set_control: std_logic_vector(7 downto 0) := "00000000";
18
set_subsec:std_logic_vector(7downto0):="00000000"; --0.00sec
19
set_sec: std_logic_vector(7 downto 0) := "00000000"; --00 sec
