Hardware Reference
In-Depth Information
20 set_min: std_logic_vector(7 downto 0) := "00110000"; --30 min
21 set_hour: std_logic_vector(7 downto 0) := "00010011"; --13 h
22 set_date: std_logic_vector(7 downto 0) := "00100101"; --date 25
23 set_month:std_logic_vector(7downto0):="00010010"); --month12
24 port (
25 --Clock and control ports:
26 clk, rst, wr, rd: in std_logic;
27 --I2C ports:
28 SCL, CH_RSTn: out std_logic;
29 SDA: inout std_logic;
30 --Display ports (test circuit):
31 ssd_1sec: out std_logic_vector(6 downto 0); --units of seconds
32 ssd_10sec: out std_logic_vector(6 downto 0); --tens of seconds
33 ssd_1min: out std_logic_vector(6 downto 0); --units of minutes
34 ssd_10min: out std_logic_vector(6 downto 0); --tens of minutes
35 ssd_1hour: out std_logic_vector(6 downto 0); --units of hours
36 ssd_10hour: out std_logic_vector(6 downto 0)); --tens of hours
37 end entity;
38 -------------------------------------------------------------------------
39 architecture moore_fsm of RTC_with_I2C_bus is
40
41
--FSM-related declarations:
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type state is (
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--common states:
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idle, start, slave_addr_wr, ack1, stop, hold,
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--write-only states:
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initial_addr_wr, ack2, wr_data, ack3,
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--read-only states:
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initial_addr_rd, ack4, restartL, restartR, slave_addr_rd, ack5,
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rd_sec, ack6, rd_min, ack7, rd_hour, no_ack);
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signal pr_state, nx_state: state;
51
52
--Auxiliary-register-related declarations:
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signal i, i_reg: natural range 0 to 8;
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signal j, j_reg: natural range 0 to 7;
55
56
--Other declarations:
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signal i2c_clk: std_logic;
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signal sec: std_logic_vector(7 downto 0);
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signal min: std_logic_vector(7 downto 0);
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signal hour: std_logic_vector(7 downto 0);
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type data_array is array (0 to 6) of std_logic_vector(7 downto 0);
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constantdata_out:data_array:=(set_control,set_subsec,set_sec,
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set_min, set_hour, set_date, set_month);
64
65 begin
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CH_RSTn <= not rst; --chip reset
68
69
--i2c_clk (100kHz):
70
process (clk)
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variable count: natural range 0 to fclk/(2*data_rate);
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begin
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if rising_edge(clk) then
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count := count + 1;
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if count=fclk/(2*data_rate) then
