Additional Design Examples - Finite State Machines in Hardware - page 299

VHDL Code
Because of space limitations, only the VHDL code is presented. However, with this
code and the SystemVerilog codes seen in chapters 7, 10, and 13, writing the corre-
sponding SystemVerilog code is relatively simple.
A complete VHDL code for the FSM of i gure 14.14 is presented below. Because it
is a category 3 machine, it was based on the template of section 12.2.
Initially, a function called bcd_to_ssd , to convert BCD (binary-coded decimal) values
into SSD values (display driver), was built in a separate package (called my_functions ),
which is called in the main code (lines 252-257) to make the corresponding
conversions.
The entity, called RTC_with_I2C_bus , is in lines 6-37. A number of system param-
eters were entered as generic constants (lines 7-23), including the clock frequency (50
MHz, line 9) and the desired I 2 C speed (100 kbps, line 10), so the I 2 C clock ( i2c_clk )
is automatically adjusted (in lines 71 and 75) when these parameters change. They
also include the RTC addresses of interest (lines 12-15) and the time and date to be
stored in the RTC registers (lines 17-23).
The circuit ports, all of type std_logic or std_logic_vector (industry standard), are in
lines 24-36. They are exactly as in i gure 14.12b.
The architecture, called moore_fsm , is in lines 39-259. As usual, it contains a declara-
tive part and a statements part, both commented on below.
The declarative part of the architecture (lines 41-63) contains FSM-related and
auxiliary-register-related declarations plus other system declarations. In the FSM dec-
larations (lines 42-50), the enumerated type state is created to represent the machine's
present and next states. In the auxiliary-register declarations (lines 53-54), the signals
needed to build the pointers i and j are created. Finally, the other declarations (lines
57-63) include the I 2 C clock, the signals that will store the values read from the RTC
(test circuit), and also a 1D 1D type called data_array , used to build a ROM called

data_out containing the data to be sent to the slave (to set the clock and calendar).
The statements part (lines 65-259) contains i ve processes. The i rst process (lines
70-80) produces i2c_clk , with frequency 100 kHz (desired data rate).
The second process (lines 83-94) builds the FSM's state register plus the auxiliary
registers for i and j .
The third process (lines 97-237) implements the entire combinational logic section
of the FSM, following the state transition diagram of i gure 14.14 exactly. Note that
because some of the output values are repeated a number of times, they were entered
as default values in lines 100-102, so the actual list of outputs (SCL , SDA , i , j ) is indeed
exactly the same in all states.
The fourth and i nal process (lines 240-251) plus associated statements (lines
252-257) constitute the test circuit. It stores the data read from the RTC and sends it
to the display.

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