Hardware Reference
In-Depth Information
Figure 14.11
Typical FSM structure for I
2
C master implementations.
reading is not wanted) and for a time equal to
t
BUF
before a new transmission can take
place. Because this diagram is completely generic, it can be used as the basis for any
circuit that writes/reads data to/from any I
2
C-interfaced device.
14.2.4 Typical FSM Structure for I
2
C Applications
Figure 14.11 shows a typical FSM structure for implementing an I
2
C master circuit.
The sequence of states is based directly on i gures 14.9 and 14.10. The process starts
when a
wr
= '1' or
rd
= '1' pulse is received, with the i rst three states after the idle
state corresponding to the initialization sequence (down to line 1 of i gure 14.9). After
this point the upper branch is pursued if writing is wanted, or the lower branch if
reading is intended.
Understanding this state transition diagram well is very important because basically
the only changes from one I
2
C application to another are in the data-write and data-
read sequences inside the dashed rectangles. Two very important aspects of this
machine are commented on below.
The i rst point regards the duration of the
wr
and
rd
signals. Note that these signals
are used to make decisions in two points along the FSM, so at least one of them must
last up to the point where the second decision must be made. If
wr
and
rd
are short
pulses, then a stretcher (section 8.11.10) can be used; another (simpler) solution is to
repeat the three initial states for writing and for reading. If, on the other hand,
wr
and
rd
are long pulses, then the
hold
state (which waits also for
t
BUF
) shown after
stop
can
solve the problem.
The second point regards the two blocks within dashed rectangles. If the number
of bytes to be transmitted or received is small, then one pair “write-data + ack” or
“read-data + ack” can be used for each byte. However, for a large number of bytes, it
is more practical to build a loop to have the same pair repeated a number of times
(except for the last pair when reading data, because then no-ack must be used in place
of ack). Both solutions can be implemented with a category 2 machine (based on the
