Hardware Reference
In-Depth Information
Figure 14.12
(a) PCF8593 pinout. (b) Setup for the experiment.
material in section 8.7), or with a category 3 machine (based on the material in section
11.5), or still using the pointer-based technique described in chapter 15. In the design
example shown next, a category 3 machine is used, with individual pairs for reading
and a looped pair for writing.
14.2.5 Complete Design Example: RTC (Real-Time Clock) Interface
This section shows a complete design example for an I
2
C master that interfaces with
an RTC (real-time clock) circuit. The master i rst writes the current time and date to
the RTC; then it reads the clock-related data continuously, hence having the RTC
operate as a high-precision clock. The circuit is implemented with VHDL and physi-
cally tested in the FPGA development board.
The RTC employed in this example is the PFC8593 (see i gure 14.12a), from NXP,
which contains clock, calendar, timer, and alarm features (see the device's manual).
The setup for the experiment is shown in i gure 14.12b. The inputs are the
wr
and
rd
commands plus the traditional clock and reset. The output is divided into two sets;
the i rst set contains
SCL
and
SDA
(plus a chip-reset signal), thus constituting the
actual I
2
C bus; the second set of outputs is for testing the circuit, displaying on six
SSDs (or on an LCD) the data (clock information) read from the RTC. The FSM i rst
writes the time and date into the RTC; then it reads continuously the clock-related
data produced by the RTC.
The 16 registers (each eight bits long) of the PCF8593 RTC are detailed in i gure
14.13. Register 0 is used for setup information; register 1 stores subseconds, with units
of subseconds in bits 3:0, and tens of subseconds in bits 7:4; register 2 stores seconds,
with units of seconds (0 to 9 values) in bits 3:0, and tens of seconds (values from 0
to 5) in bits 7:4; and so on.
