Hardware Reference
In-Depth Information
The architecture, called
moore_fsm
, is in lines 14-214. As usual, it contains a declara-
tive part and a statements part, both commented below.
The declarative part of the architecture (lines 16-43) starts with a function that
converts binary-coded decimal (BCD) values into LCD characters (according to i gure
14.3). It also contains FSM-related and other signal declarations. In the FSM declara-
tions (lines 35-39), the enumerated type
state
is created to represent the machine's
present and next states. The other declarations contain in line 42 the signals needed
to interface the Clock block with the LCD block (see i gure 14.5) and in line 43 a
signal that will allow the adoption of different limits in the i rst clock counter so the
clock can be sped up during seconds, minutes, or hours adjustments.
The code proper (statements part, lines 45-214) is divided into two parts. Part I
(lines 47-110) implements the Clock block of i gure 14.5, while part II (lines 112-212)
implements the LCD Driver block of i gure 14.5.
Part I (Clock block) contains just dei nitions for the speed-up factors (lines 50-53)
and a basic process (lines 56-110) that implements the clock proper.
Part II (LCD Driver block) starts with dei nitions for the LCD static signals (lines
114-116), followed by a process (lines 119-129) that creates the 500 Hz clock for the
LCD controller. The last two processes implement the FSM that runs the LCD, with
the sequential section (FSM state register) in lines 132-139 and the combinational
logic section in lines 142-212, based directly on the template of section 6.3. Note that
this last process follows i gure 14.4 exactly.
Finally, observe the correct use of registers and the completeness of the code, as
described in comment 10 of section 6.3.
The reader is invited to set up this (or an equivalent) experiment and play with it
in the FPGA board.
1 ----------------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 ----------------------------------------------------------------
5 entity clock_with_LCD_display is
6 generic (fclk: natural := 50_000_000); --freq in Hz
7 port (
8 clk, rst_clock, rst_lcd, sec, min, hour: in std_logic;
9 RS, RW, LCD_ON, BKLT_ON: out std_logic;
10 E: buffer std_logic;
11 DB: out std_logic_vector(7 downto 0));
12 end entity;
13 ----------------------------------------------------------------
14 architecture moore_fsm of clock_with_LCD_display is
15
16
--BCD-to-LCD character conversion function:
17
function bcd_to_lcd (input: natural) return std_logic_vector is
18
begin
19
case input is
