Hardware Reference
In-Depth Information
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when 0 => return "00110000"; --"0" on LCD
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when 1 => return "00110001"; --"1" on LCD
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when 2 => return "00110010"; --"2" on LCD
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when 3 => return "00110011"; --"3" on LCD
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when 4 => return "00110100"; --"4" on LCD
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when 5 => return "00110101"; --"5" on LCD
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when 6 => return "00110110"; --"6" on LCD
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when 7 => return "00110111"; --"7" on LCD
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when 8 => return "00111000"; --"8" on LCD
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when 9 => return "00111001"; --"9" on LCD
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when others => return "00111111"; --"?" on LCD
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end case;
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end bcd_to_lcd;
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--FSM-related declarations:
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type state is (FunctionSet1, FunctionSet2, FunctionSet3,
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FunctionSet4, ClearDisplay, DisplayControl, EntryMode,
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WriteHourT, WriteHourU, WriteColon1, WriteMinT, WriteMinU,
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WriteColon2, WriteSecT, WriteSecU, ReturnHome);
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signal pr_state, nx_state: state;
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--Other signal declarations:
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signal secU, secT, minU, minT, hourU, hourT: natural range 0 to 9;
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signal limit: natural range 0 to fclk;
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45 begin
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--PART I: CLOCK BLOCK--------------------------
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--Speed-up factors:
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limit <= fclk/8192 when hour='1' else
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fclk/256 when min='1' else
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fclk/8 when sec='1' else
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fclk;
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--Clock design:
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process (clk, rst_clock)
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variable counter1: natural range 0 to fclk;
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variable counter2: natural range 0 to 10;
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variable counter3: natural range 0 to 6;
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variable counter4: natural range 0 to 10;
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variable counter5: natural range 0 to 6;
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variable counter6: natural range 0 to 10;
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variable counter7: natural range 0 to 3;
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begin
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if rst_clock='1' then
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counter1 := 0;
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counter2 := 0;
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counter3 := 0;
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counter4 := 0;
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counter5 := 0;
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counter6 := 0;
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counter7 := 0;
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elsif rising_edge(clk) then
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counter1 := counter1 + 1;
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if counter1=limit then
