Additional Design Examples - Finite State Machines in Hardware - page 285

Figure 14.5
Digital clock with LCD display.
The outputs of the Clock block are the following:
— secU : Units of seconds.
— secT : Tens of seconds.
— minU : Units of minutes.
— minT : Tens of minutes.
— hourU : Units of hours.
— hourT : Tens of hours.
Finally, the outputs of the LCD Driver block are the signals already described (listed
in i gure 14.1b):
— E (enable): Actual LCD clock.
— RS (register select): Selects LCD instruction ('1') or data ('0') register.
— R/W (read/write): Selects LCD read ('1') or write ('0') operation.
— DB (data bus): Bidirectional eight-bit bus.
— LCD_ON : Turns display on ('1') or off ('0').
— BKLT_ON : Turns backlight on ('1') or off ('0').
VHDL Code
Because of space limitations, only the VHDL code is presented. However, with that
code and the SystemVerilog codes seen in chapters 7, 10, and 13, writing the corre-
sponding SystemVerilog code is relatively simple.
A complete VHDL code for the FSM of i gure 14.4b, with the initialization sequence
of i gure 14.4a, is presented below. Because it is a category 1 machine, it was based on
the template of section 6.3.
The entity, called clock_with_LCD_display , is in lines 5-12. The clock frequency was
entered as a generic constant (line 6), so the speed-up factors (lines 50-53), the 1-s
time base for the clock (line 57), and the frequency of the LCD clock (500 Hz, lines
120 and 124) will adjust automatically when this parameter changes. The circuit ports
(lines 8-11) are exactly as in i gure 14.5 and are all of type std_logic or std_logic_vector
(industry standard).