Hardware Reference
In-Depth Information
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//FSM state register:
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always_ff @(posedge clk, posedge rst)
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if (rst) pr_state <= idle;
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else pr_state <= nx_state;
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//FSM combinational logic:
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always_comb begin
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case (pr_state)
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idle: begin
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A <= 0;
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WEn <= 1'b1;
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done_wr <= 1'b1;
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done_rd <= 1'b1;
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tmax <= 0;
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if (wr & ~rd) nx_state <= write1;
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else if (~wr & rd) nx_state <= read1;
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else nx_state <= idle;
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end
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write1: begin
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A <= A_reg;
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WEn <= 1'b0;
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done_wr <= 1'b0;
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done_rd <= 1'b1;
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tmax <= 0;
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nx_state <= write2;
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end
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write2: begin
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A <= A_reg + 1;
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WEn <= 1'b1;
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done_wr <= 1'b0;
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done_rd <= 1'b1;
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tmax <= 0;
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if (A <= Amax) nx_state <= write1;
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else nx_state <= hold;
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end
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read1: begin
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A <= A_reg;
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WEn <= 1'b1;
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done_wr <= 1'b1;
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done_rd <= 1'b0;
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tmax <= Tread;
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if (t>=tmax) nx_state <= read2;
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else nx_state <= read1;
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end
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read2: begin
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A <= A_reg + 1;
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WEn <= 1'b1;
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done_wr <= 1'b1;
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done_rd <= 1'b0;
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tmax <= 0;
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if (A <= Amax) nx_state <= read1;
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else nx_state <= hold;
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end
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hold: begin
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A <= 0;
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WEn <= 1'b1;
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done_wr <= 1'b1;
