Hardware Reference
In-Depth Information
21 //Declarations:-----------------------------------
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//FSM-related declarations:
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typedef enum logic [2:0]
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{idle, write1, write2, read1, read2, hold} state;
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state pr_state, nx_state;
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//Auxiliary-register-related declarations:
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logic [Abus-1:0] A_reg;
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//Timer-related declarations:
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logic [$clog2(Tread)-1:0] t, tmax; //rangeā„Tread
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//Function construction:
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function [6:0] integer_to_ssd;
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input [3:0] inp;
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case (inp)
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0: integer_to_ssd = 7'b0000001;
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1: integer_to_ssd = 7'b1001111;
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2: integer_to_ssd = 7'b0010010;
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3: integer_to_ssd = 7'b0000110;
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4: integer_to_ssd = 7'b1001100;
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5: integer_to_ssd = 7'b0100100;
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6: integer_to_ssd = 7'b0100000;
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7: integer_to_ssd = 7'b0001111;
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8: integer_to_ssd = 7'b0000000;
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9: integer_to_ssd = 7'b0000100;
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10: integer_to_ssd = 7'b0001000;
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11: integer_to_ssd = 7'b1100000;
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12: integer_to_ssd = 7'b0110001;
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13: integer_to_ssd = 7'b1000010;
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14: integer_to_ssd = 7'b0110000;
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15: integer_to_ssd = 7'b0111000;
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default: integer_to_ssd = 7'b1111110;
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endcase
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endfunction
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58 //Statements:--------------------------------------
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//Static SRAM signals:
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assign CEn = 1'b0;
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assign OEn = 1'b0;
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assign UBn = 1'b0;
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assign LBn = 1'b0;
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//Timer (using strategy #2):
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always_ff @(posedge clk, posedge rst)
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if (rst) t <= 0;
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else if (t < tmax) t <= t + 1;
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else t <= 0;
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// Auxiliary register:
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always_ff @(posedge clk, posedge rst)
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if (rst) A_reg <= 0;
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else A_reg <= A;
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