Hardware Reference
In-Depth Information
134
done_rd <= 1'b1;
135
tmax <= 0;
136
if (~wr & ~rd) nx_state <= idle;
137
else nx_state <= hold;
138
end
139
endcase
140
141
//In-out port with tri-state:
142
if (~done_wr) D <= A[7:0] + seed;
143
else D <= 'z;
144
145
//SSD signal produced by function integer_to_ssd:
146
ssd <= integer_to_ssd(D[3:0]);
147
end
148
149 endmodule
150 //-----------------------------------------------
13.7 Exercises
Exercise 13.1: Long-String Comparator #1
Solve exercise 12.1 using SystemVerilog instead of VHDL.
Exercise 13.2: Long-String Comparator #2
Solve exercise 12.2 using SystemVerilog instead of VHDL.
Exercise 13.3: Hamming-Weight Calculator
Solve exercise 12.3 using SystemVerilog instead of VHDL.
Exercise 13.4: Leading-Ones Counter
Solve exercise 12.4 using SystemVerilog instead of VHDL.
Exercise 13.5: Complete Reference-Value Defi ner
Solve exercise 12.5 using SystemVerilog instead of VHDL.
Exercise 13.6: Factorial Calculator
Solve exercise 12.6 using SystemVerilog instead of VHDL.
Exercise 13.7: Divider
Solve exercise 12.7 using SystemVerilog instead of VHDL.
