Hardware Reference
In-Depth Information
31
32
//FSM state register:
33
always_ff @(posedge clk, posedge rst)
34
if (rst) pr_state <= idle;
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else pr_state <= nx_state;
36
37
//FSM combinational logic:
38
always_comb
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case (pr_state)
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idle: begin
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i <= 1'b0;
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y <= y_reg;
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done <= 1'b1;
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if (dv & ~x) nx_state <= load0;
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else if (dv & x) nx_state <= load1;
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else nx_state <= idle;
47
end
48
load0: begin
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i <= i_reg + 1;
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y <= y_reg;
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y[i-1] <= 1'b0;
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done <= 1'b0;
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if (i=N) nx_state <= idle;
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else if (x) nx_state <= load1;
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else nx_state <= load0;
56
end
57
load1: begin
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i <= i_reg + 1;
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y <= y_reg;
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y[i-1] <= 1'b1;
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done <= 1'b0;
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if (i=N) nx_state <= idle;
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else if (~x) nx_state <= load0;
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else nx_state <= load1;
65
end
66
endcase
67
68 endmodule
69 //-----------------------------------------------------------
13.6 Design of a Memory Interface
This section presents a SystemVerilog-based design for the memory interface intro-
duced in section 11.7.8 (i gure 11.16). The SRAM used in the experiments is the
IS61LV25616 device, from ISSI, which is capable of storing 262k 16-bit words. The
corresponding FSM was presented in i gure 11.16c, and the circuit ports are depicted
in i gure 13.1 (note that a test circuit has been included).
The i rst part of the code (
module header
) is in lines 1-19. The module's name is
sram_interface
. Several global parameters were included for both the main circuit and
a test circuit. The port names are from i gure 13.1. All ports are of type
logic
.
