Hardware Reference
In-Depth Information
output values are unique because in a Moore machine the outputs depend only on
the state in which the machine is. Another important aspect can be observed in lines
50-51 and 59-60; note that i rst a value is assigned to the entire vector y (lines 50 and
59); then one of its bits, y ( i
1), is overwritten (lines 51 and 60).
In this kind of application, glitches during clock transitions are generally not a
problem. Anyway, because y is one of the signals that go through an auxiliary register,
if a glitch-free (pipelined) output is required, we can simply send out y_reg instead of y .
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values/expressions are always properly declared; 3) the
specii cations for nx_state are always i nalized with an else statement, so no condition
is left unchecked.
The number of l ip-l ops inferred by the compiler on synthesizing the code below,
with regular sequential encoding (section 3.7) and N = 8, was 14.
Simulation results from this code are exactly the same as those obtained using
VHDL, shown in i gure 12.2.
1 //Module header:--------------------------------------------
2 module serial_data_receiver
3
#(parameter N=8) //number of bits (any >0)
4
(
5
input logic x, dv, clk, rst,
6
output logic done,
7
output logic [N-1:0] y);
8
9 //Declarations:----------------------------------------------
10
11
//FSM-related declarations:
12
typedef enum logic [1:0] {idle, load0, load1} state;
13
state pr_state, nx_state;
14
15
//Auxiliary-register-related declarations:
16
logic [N-1:0] y_reg;
17
logic [$clog2(N):0] i, i_reg; //function ceiling(log2(N))
18
19 //Statements:------------------------------------------------
20
21
//Auxiliary register:
22
always_ff @(posedge clk, posedge rst)
23
if (rst) begin
24
i_reg <= '0;
25
y_reg <= '0;
26
end
27
else begin
28
i_reg <= i;
29
y_reg <= y;
30
end
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