Hardware Reference
In-Depth Information
56
end
57
nop: begin
58
i <= i_reg;
59
nx_state <= shift;
60
end
61
add: begin
62
wrR2 <= 'b1;
63
ALUop <= 2'b11;
64
i <= i_reg;
65
nx_state <= shift;
66
end
67
shift: begin
68
shft <= 'b1;
69
i <= i_reg + 1;
70
if (i<N) nx_state <= waitt;
71
else nx_state <= idle;
72
end
73
endcase
74
75 endmodule
76 //-----------------------------------------------------------
13.5 Design of a Serial Data Receiver
This section presents a SystemVerilog-based design for the serial data receiver intro-
duced in section 11.7.7. The Moore template for category 3 machines seen in section
13.2 is used to implement the solution of i gure 11.14c.
The i rst part of the code (
module header
) is in lines 1-7. The module's name is
serial_data_receiver
. Note that all ports are of type
logic
.
The second part of the code (
declarations
) is in lines 9-17. In the FSM-related dec-
larations (lines 12-13), the enumerated type
state
is created to represent the machine's
present and next states. In the auxiliary-register-related declarations (lines 16-17),
y_
reg
,
i,
and
i_reg
are created to deal with the auxiliary registers. Note that two auxiliary
registers are needed in this example: for the main (actual) output (
y
) and for the output
that operates as an auxiliary pointer (
i
) to the FSM.
The third and i nal part of the code (
statements
) is in lines 19-68. It contains three
always
blocks, described next.
The i rst
always
block (lines 22-30) is an
always_ff
that implements the auxiliary
register, similarly to the template.
The second
always
block (lines 33-35) is another
always_ff
, which implements
the machine's state register, exactly as in the template.
The third and i nal
always
block (lines 38-66) is an
always_comb
, which imple-
ments the entire combinational logic section. It is just a list of all states, each contain-
ing the output values and the next state. Observe that in the (originally) recursive
equations (lines 42, 49-50, and 58-59),
i_reg
and
y_reg
appear on the right-hand side
instead of
i
and
y
themselves (as proposed in the template). As usual, in each state the
