Hardware Reference
In-Depth Information
multiplier. The Moore template for category 3 machines seen in section 13.2 is used
to implement the FSM of i gure 11.12b.
The i rst part of the code (
module header
) is in lines 1-7. The module's name is
contol_unit_for_multiplier
. Note that all ports are of type
logic
.
The second part of the code (
declarations
) is in lines 9-17. In the FSM-related dec-
larations (lines 12-14), the enumerated type
state
is created to represent the machine's
present and next states. In the auxiliary-register-related declarations (line 17),
i
and
i_reg
are created to deal with the auxiliary register. Note that in this example none of
the actual outputs is stored in an auxiliary register (the auxiliary registers are always
for the variables that appear in the recursive equations).
The third and i nal part of the code (
statements
) is in lines 19-75. It contains three
always
blocks, described next.
The i rst
always
block (lines 22-24) is an
always_ff
that implements the auxiliary
register, exactly as in the template.
The second
always
block (lines 27-29) is another
always_ff
, which implements
the machine's state register, again exactly as in the template.
The third and i nal
always
block (lines 32-73) is an
always_comb
, which imple-
ments the entire combinational logic section. It is just a list of all states, each contain-
ing the output values and the next state. Note that because some of the output values
get repeated several times, default values were entered in lines 35-40, so they only
need to be included in the
case
statement when different values are required. Observe
that in the (originally) recursive equations (lines 53, 58, 64, and 69),
i_reg
appears on
the right-hand side instead of
i
itself (as proposed in the template). As usual, in each
state the output values are unique because in a Moore machine the outputs depend
only on the state in which the machine is.
In datapath-related designs, possible glitches at the output of the control unit fol-
lowing clock transitions are normally not a problem, so the optional output register
was not employed.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values/expressions are always properly declared; 3) any
conditional specii cation for
nx_state
is i nalized with an
else
statement, so no condi-
tion is left unchecked.
The number of l ip-l ops inferred by the compiler on synthesizing the code below,
with regular sequential encoding (section 3.7), was six for
N
= 4 and nine for
N
= 32
bits. Compare these results against your predictions made in exercise 11.10.
Simulation results from this code are exactly the same as those obtained using
VHDL, shown in i gure 12.1.
