Hardware Reference
In-Depth Information
20
// Auxiliary register:
21
(same as for category 3 Moore, section 13.2)
22
23
//FSM state register:
24
(same as for category 3 Moore, section 13.2)
25
26
//FSM combinational logic:
27
always_comb
28
case (pr_state)
29
A:
30
if (condition) begin
31
outp <= outp_reg;
32
tmax <= <value>; //if using strategy #2
33
nx_state <= B;
34
end
35
else if (condition) begin
36
outp <= outp_reg + 1;
37
tmax <= <value>; //if using strategy #2
38
nx_state <= ...;
39
end
40
else begin
41
outp <= <value>;
42
tmax <= <value>;
43
nx_state <= A;
44
end
45
B:
46
if (condition) begin
47
outp <= outp_reg + 1;
48
tmax <= <value>;
49
nx_state <= C;
50
end
51
else if (condition) begin
52
outp <= outp_reg;
53
tmax <= <value>;
54
nx_state <= ...;
55
end
56
else begin
57
outp <= <value>;
58
tmax <= <value>;
59
nx_state <= B;
60
end
61
C: ...
62
...
63
endcase
64
65
//Optional output register:
66
(same as for category 3 Moore, section 13.2)
67
68 endmodule
69 //-------------------------------------------------
13.4 Design of a Datapath Controller for a Multiplier
This section presents a SystemVerilog-based design for the control unit introduced
in section 11.7.5, which controls a datapath to produce a sequential add-and-shift
