Hardware Reference
In-Depth Information
103
--FSM combinational logic:
104
process (all)
105
begin
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case pr_state is
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when idle =>
108
addr <= 0;
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WEn <= '1';
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done_wr <= '1';
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done_rd <= '1';
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tmax <= 0;
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if wr='1' and rd='0' then
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nx_state <= write1;
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elsif wr='0' and rd='1' then
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nx_state <= read1;
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else
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nx_state <= idle;
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end if;
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when write1 =
>
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addr
<
= addr_reg;
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WEn <= '0';
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done_wr <= '0';
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done_rd <= '1';
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tmax <= 0;
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nx_state <= write2;
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when write2 =>
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addr <= addr_reg + 1;
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WEn <= '1';
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done_wr <= '0';
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done_rd <= '1';
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tmax <= 0;
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if addr <= Amax then
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nx_state <= write1;
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else
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nx_state <= hold;
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end if;
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when read1 =>
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addr <= addr_reg;
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WEn <= '1';
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done_wr <= '1';
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done_rd <= '0';
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tmax <= Tread;
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if t>=tmax then
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nx_state <= read2;
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else
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nx_state <= read1;
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end if;
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when read2 =
>
150
addr
<
= addr_reg + 1;
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WEn <= '1';
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done_wr <= '1';
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done_rd <= '0';
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tmax <= 0;
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if addr <= Amax then
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nx_state <= read1;
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else
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nx_state <= hold;
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end if;
