Hardware Reference
In-Depth Information
46
when 3 => output:="0000110";
47
when 4 => output:="1001100";
48
when 5 => output:="0100100";
49
when 6 => output:="0100000";
50
when 7 => output:="0001111";
51
when 8 => output:="0000000";
52
when 9 => output:="0000100";
53
when 10 => output:="0001000";
54
when 11 => output:="1100000";
55
when 12 => output:="0110001";
56
when 13 => output:="1000010";
57
when 14 => output:="0110000";
58
when 15 => output:="0111000";
59
when others => output:="1111110"; --"-"
60
end case;
61
return output;
62
end integer_to_ssd;
63
64 begin
65
66
--Static SRAM signals:
67
CEn<='0'; OEn<='0'; UBn<='1'; LBn<='0';
68
69 --Timer (using strategy #2, section 8.5.3):
70 process (clk, rst)
71 begin
72 if (rst='1') then
73 t <= 0;
74 elsif rising_edge(clk) then
75 if t < tmax then
76 t <= t + 1;
77 else
78 t <= 0;
79 end if;
80 end if;
81 end process;
82
83
--Auxiliary register:
84
process (clk, rst)
85
begin
86
if rst='1' then
87
addr_reg <= 0;
88
elsif rising_edge(clk) then
89
addr_reg <= addr;
90
end if;
91
end process;
92
93
--FSM state register:
94
process (clk, rst)
95
begin
96
if rst='1' then
97
pr_state <= idle;
98
elsif rising_edge(clk) then
99
pr_state
<
= nx_state;
100
end if;
101
end process;
102
