VHDL Design of Recursive (Category 3) State Machines - Finite State Machines in Hardware - page 261

160 when hold =>

161 addr <= 0;

162 WEn <= '1';

163 done_wr <= '1';

164 done_rd <= '1';

165 tmax <= 0;

166 if wr='0' and rd='0' then

167 nx_state <= idle;

168 else

169 nx_state <= hold;

170 end if;

171 end case;

172 end process;

173
174

A <= conv_std_logic_vector(addr, Abus);

175
176 --Test circuit:

177 D < = seed + conv_std_logic_vector(addr, 8) when done_wr='0' else

178 (others => 'Z');

179 ssd <= int_to_ssd(conv_integer(D));

180
181 end architecture;
182 ------------------------------------------------------------------

12.7 Exercises

Exercise 12.1: Long-String Comparator #1
This exercise concerns the long-string comparator of i gure 11.6, which must detect
whether the last N bits in two serial bit streams are equal.

a) Implement it using VHDL. Compile it for N = 64 bits and sequential encoding and
check if the number of DFFs inferred by the compiler matches the estimate made in
section 11.7.2.
b) Recompile it for N = 4; then simulate it using the same stimuli of i gure 11.6c and
check if the same waveforms result.

Exercise 12.2: Long-String Comparator #2
This exercise concerns the long-string comparator of exercise 11.5.

a) Solve exercise 11.5 if not done yet.
b) Implement the resulting FSM using VHDL. Check if the number of DFFs inferred
by the compiler matches your estimate.
c) Simulate it using the same stimuli of i gure 11.19, checking if the same waveforms
result.

Exercise 12.3: Hamming-Weight Calculator
This exercise concerns the Hamming-weight calculator of exercise 11.3.