Hardware Reference
In-Depth Information
9 wrR1, sel, wrR2, shft: out std_logic;
10 ALUop: out std_logic_vector(1 downto 0));
11 end entity;
12 -----------------------------------------------------------
13 architecture moore_fsm of control_unit_for_multiplier is
14
15
--FSM-related declarations:
16
type state is (idle, load, waitt, nop, add, shift);
17
signal pr_state, nx_state: state;
18
19
--Auxiliary-register-related declarations:
20
signal i, i_reg: natural range 0 to N;
21
22 begin
23
24
--Auxiliary register:
25
process (clk, rst)
26
begin
27
if rst='1' then
28
i_reg <= 0;
29
elsif rising_edge(clk) then
30
i_reg <= i;
31
end if;
32
end process;
33
34
--FSM state register:
35
process (clk, rst)
36
begin
37
if rst='1' then
38
pr_state <= idle;
39
elsif rising_edge(clk) then
40
pr_state
<
= nx_state;
41
end if;
42
end process;
43
44
--FSM combinational logic:
45
process (all)
46
begin
47
--Default values:
48
wrR1 <= '0';
49
sel <= '0';
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wrR2 <= '0';
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shft <= '0';
52
ALUop <= "00";
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i <= 0;
54
--Case statement:
55
case pr_state is
56
when idle =>
57
if dv='1' then
58
nx_state <= load;
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else
60
nx_state
<
= idle;
61
end if;
62
when load =
>
63
wrR1
<
= '1';
64
sel
<
= '1';
65
wrR2
<
= '1';
66
nx_state
<
= waitt;
