Hardware Reference
In-Depth Information
67
when waitt =>
68
i <= i_reg;
69
if prod='0' then
70
nx_state <= nop;
71
else
72
nx_state <= add;
73
end if;
74
when nop =>
75
i <= i_reg;
76
nx_state <= shift;
77
when add =>
78
wrR2 <= '1';
79
ALUop <= "11";
80
i <= i_reg;
81
nx_state <= shift;
82
when shift =>
83
shft <= '1';
84
i <= i_reg + 1;
85
if i<N then
86
nx_state <= waitt;
87
else
88
nx_state <= idle;
89
end if;
90
end case;
91
end process;
92
93 end architecture;
94 -----------------------------------------------------------
The number of l ip-l ops inferred by the compiler on synthesizing the code above,
with regular sequential encoding (section 3.7), was six for
N
= 4 and nine for
N
= 32
bits. Compare these results against your predictions made in exercise 11.10.
Simulation results are shown in i gure 12.1. Observe in the plot for
prod
that the
circuit was tested for the sequence
prod
= {'1', '0', '1', '0'}, so the expected sequence
of states is
pr_state
= {0, 1, 2, 4, 5, 2, 3, 5, 2, 4, 5, 2, 3, 5, 0}, which indeed occurs (recall
that the states are enumerated in the order that they appear in line 16; however, some
compilers reserve the value zero for the reset state, but that is not a concern here
because that is the i rst state in our list anyway). Note that the values produced at the
output in each state are exactly as in i gure 11.12b. Finally, compare these simulation
results against your sketch in exercise 11.10 to see whether they match.
12.5 Design of a Serial Data Receiver
This section presents a VHDL-based design for the serial data receiver introduced in
section 11.7.7. The Moore template for category 3 machines seen in section 12.2 is
used to implement the solution of i gure 11.14c.
The entity, called
serial_data_receiver
, is in lines 5-11. The number of bits (
N
) is
entered as a generic parameter (line 6). All ports (lines 8-10) are of type
std_logic
or
