Hardware Reference
In-Depth Information
are created to deal with the auxiliary register (note that in this case none of the actual
outputs is stored in an auxiliary register).
The i rst process (lines 25-32) implements the auxiliary register, exactly as in the
template.
The second process (lines 35-42) implements the FSM's state register, again exactly
as in the template.
The third and i nal process (lines 45-91) implements the entire combinational logic
section. It is just a list of all states, each containing the output values and the next
state. Note that because some of the output values get repeated several times, default
values were entered in lines 48-53, so they only need to be included in the
case
state-
ment when different values are required (see section 6.4.3). Observe that in the (origi-
nally) recursive equations (lines 68, 75, 80, and 84),
i_reg
appears on the right-hand
side instead of
i
itself (as seen in the template). As usual, in each state the output value
is unique because in a Moore machine the output depends only on the state in which
the machine is.
In datapath-related designs, possible glitches at the output of the control unit
during clock transitions are normally not a problem, so the optional output register
is not employed.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 39 (responsible for the inference of
l ip-l ops), which is closed in line 41, guaranteeing that only the machine state (line
40) gets stored (the auxiliary register is a separate circuit, built in the preceding
process). The outputs are in the next process, which is purely combinational (thus not
registered).
2) Regarding the outputs: The list of outputs (
wrR1
,
sel
,
wrR2
,
shft
,
ALUop
,
i
) is exactly
the same in all states, and the corresponding values/expressions are always properly
declared (note that some values are declared in the default list of lines 48-53).
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 56, 62, 67, . . .), and in each state the conditional declarations for
the next state are always i nalized with an
else
statement (lines 59, 71, 87), guarantee-
ing that no condition is left unchecked.
1 -----------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -----------------------------------------------------------
5 entity control_unit_for_multiplier is
6
generic (N: natural := 4); --number of bits (any >0)
7
port (
8
dv, prod, clk, rst: in std_logic;
