Hardware Reference
In-Depth Information
37
end
38
B: begin
39
outp1 <= <value>;
40
outp2 <= <value>;
41
...
42
if (... and t>=T3-1) nx_state <= C;
43
else if (...) nx_state <= ...;
44
else nx_state <= B;
45
end
46
C: begin
47
...
48
end
49
...
50
endcase
51
52
//Optional output register:
53
(same as for category 1 Moore, section 7.3)
54
55 endmodule
56 //----------------------------------------------------------
The next template is for timed Moore machines employing strategy #2 to imple-
ment the timer.
The i rst difference is in line 14, which now includes also
t
max
.
The second difference is in the
always_ff
block for the timer (lines 19-22), which
is now based on the strategy described in section 8.5.3.
The third and i nal difference is in
always_comb
block that implements the FSM's
combinational logic section (lines 28-52), which requires now the value of
t
max
to be
specii ed in each state (lines 34, 43, . . .), even if the state is untimed (
t
max
= 0). This
code can obviously be simplii ed in several ways when there are no conditional-timed
transitions and/or
t
max
is the same in all or most states.
1 //Timed Moore machine with timer control strategy #2
2 //Part 1: Module header:-----------------------------
3
(same as template above)
4
5 //Part 2: Declarations:------------------------------
6
7
//FSM-related declarations:
8
(same as for category 1 Moore, section 7.3)
9
10
//Timer-related declarations:
11
const logic [7:0] T1 = <value>;
12
const logic [7:0] T2 = <value>;
13
...
14
logic [7:0] t, tmax;
15
16 //Part 3: Statements:-------------------------------
17
18
//Timer (strategy #2, section 8.5.3):
