Hardware Reference
In-Depth Information
19
always_ff @(posedge clk, posedge rst)
20
if (rst) t <= 0;
21
else if (t < tmax) t <= t + 1;
22
else t <= 0;
23
24
//FSM state register:
25
(same as for category 1 Moore, Section 7.3)
26
27
//FSM combinational logic:
28
always_comb
29
case (pr_state)
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A: begin
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outp1 <= <value>;
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outp2 <= <value>;
33
...
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tmax <= T1-1;
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if (... and t=tmax) nx_state <= B;
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else if (...) nx_state <= ...;
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else nx_state <= A;
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end
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B: begin
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outp1 <= <value>;
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outp2 <= <value>;
42
...
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tmax <= T2-1;
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if (... and t=tmax) nx_state <= C;
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else if (...) nx_state <= ...;
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else nx_state <= B;
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end
48
C: begin
49
...
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end
51
...
52
endcase
53
54
//Optional output register:
55
(same as for category 1 Moore, section 7.3)
56
57 endmodule
58 //-------------------------------------------------
10.3 SystemVerilog Template for Timed (Category 2) Mealy Machines
The template is presented below, using strategy #1 to implement the timer. The only
difference with respect to the Moore template just described is in the
always_comb
block for the combinational logic (lines 22-64) because the output is specii ed differ-
ently now. Recall that in a Mealy machine the output depends not only on the FSM's
state but also on its input, so
if
statements are expected for the output in one or more
states because the output values might not be unique. This is achieved by including
such values within the conditional statements for
nx_state
. For example, observe in
