Hardware Reference
In-Depth Information
61
62
--Optional output register:
63
(same as for Moore, section 9.2)
64
65 end architecture;
66 ---------------------------------------------------------
9.4 Design of a Light Rotator
This section presents a VHDL-based design for the light rotator introduced in
section 8.11.2. The Moore template of section 9.2 is used to implement the FSM
of i gure 8.14b. Either strategy #1 (section 8.5.2) or #2 (section 8.5.3) can be used
to build the timer (both templates were presented in section 9.2); the former is
employed in the code below, while the latter is explored in exercise 9.1.
The entity, called
light_rotator
, is in lines 5-9. All ports are of type
std_logic
or
std_
logic_vector
(industry standard).
The architecture, called
moore_fsm
, is in lines 11-105. As usual, it contains a declara-
tive part and a statements part, with three processes in the latter.
The declarative part of the architecture (lines 13-21) contains FSM- and
timer-related declarations. In the former, the enumerated type
state
is created to
represent the machine's present and next states. In the latter, the values chosen
for
T
1
and
T
2
are such that 120 ms and 35 ms result, respectively, assuming
f
clk
=
50 MHz.
The i rst process (lines 26-37) implements the timer (using strategy #1). Except for
the inclusion of
stp
(lines 26 and 30), this code is exactly as in the template.
The second process (lines 40-47) implements the FSM's state register, exactly as in
the template.
The third and i nal process (lines 50-103) implements the entire combinational
logic section. It is just a list of all states (indeed, because this code is repetitive, some
of the states were not detailed in order to save some space), each containing the output
(
ssd
) value and the next state. Note that in each state the output value is unique
because in a Moore machine the output depends only on the state in which the
machine is.
In this kind of application the “
1” term present in the determination of the total
time (lines 20, 55, 62, . . .) does not make any difference, but it was maintained as a
reminder of the accurate value.
Observe the correct use of registers and the completeness of the code, as described
in comment 10 of section 6.3. Note in particular the following:
−
1) Regarding the use of registers: The circuit is not overregistered. This can be observed
in the
elsif rising_edge(clk)
statement of line 44 (responsible for the inference of
l ip-l ops), which is closed in line 46, guaranteeing that only the machine state (line
