Hardware Reference
In-Depth Information
5 entity circuit is
6 (same as for Moore, Section 9.2));
7 end entity;
8 ---------------------------------------------------------
9 architecture mealy_fsm of circuit is
10 (same as for Moore, section 9.2)
11 begin
12
13
--Timer (using timer control strategy #1):
14
(same as for Moore, section 9.2)
15
16
--FSM state register:
17
(same as for Moore, section 9.2)
18
19
--FSM combinational logic:
20
process (all)
21
begin
22
case pr_state is
23
when A =>
24
if ... and t>=T1-1 then
25
output1 <= <value>;
26
output2 <= <value>;
27
...
28
nx_state <= B;
29
elsif ... and t>=T2-1 then
30
output1 <= <value>;
31
output2 <= <value>;
32
...
33
nx_state <= ...;
34
else
35
output1 <= <value>;
36
output2 <= <value>;
37
...
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nx_state <= A;
39
end if;
40
when B =>
41
if ... and t>=T3-1 then
42
output1 <= <value>;
43
output2 <= <value>;
44
...
45
nx_state <= C;
46
elsif ... then
47
output1 <= <value>;
48
output2 <= <value>;
49
...
50
nx_state <= ...;
51
else
52
output1 <= <value>;
53
output2 <= <value>;
54
...
55
nx_state <= B;
56
end if;
57
when C =>
58
...
59
end case;
60
end process;
