Hardware Reference
In-Depth Information
45) gets stored (the timer is in a separate circuit—see i gure 8.2a). The output (
ssd
) is
in the next process, which is purely combinational (thus not registered).
2) Regarding the outputs: The list of outputs (just
ssd
in this example) is exactly the
same in all states (see lines 54, 61, 68, . . .), and the corresponding values are always
properly declared.
3) Regarding the next state: Again, the coverage is complete because all states are
included (see lines 53, 60, 67, . . .), and in each state the next state is always properly
declared (lines 55-59, 62-66, 69-73, . . .).
The total number of l ip-l ops inferred by the compiler using the code below was
27 for sequential or Gray encoding, 29 for Johnson, and 35 for one-hot, which agree
with the predictions made in section 8.11.2.
Because this particular machine has only simple timed transitions, a few simplii ca-
tions could be made in the code below, but with no impact on the resulting circuit
(thus with no reason to depart from the proposed template).
1 -----------------------------------------------------------
2 library ieee;
3 use ieee.std_logic_1164.all;
4 -----------------------------------------------------------
5 entity light_rotator is
6 port (
7 stp, clk, rst: in std_logic;
8 ssd: out std_logic_vector(6 downto 0));
9 end entity;
10 -----------------------------------------------------------
11 architecture moore_fsm of light_rotator is
12
13
--FSM-related declarations:
14
type state is (A, AB, B, BC, C, CD, D, DE, E, EF, F, FA);
15
signal pr_state, nx_state: state;
16
17
--Timer-related declarations:
18
constant T1: natural := 6_000_000; --120ms @ fclk=50MHz
19
constant T2: natural := 1_750_000; --35ms @ fclk=50MHz
20
constant tmax: natural := T1-1; --tmax≥max(T1,T2)-1
21
signal t: natural range 0 to tmax;
22
23 begin
24
25
--Timer (using strategy #1):
26
process (clk, rst, stp)
27
begin
28
if rst='1' then
29
t <= 0;
30
elsif rising_edge(clk) and stp='0' then
31
if pr_state /= nx_state then
32
t <= 0;
33
elsif t /= tmax then
34
t <= t + 1;
