Hardware Reference
In-Depth Information
An illustrative timing diagram for this FSM is shown in i gure 8.26b. It is very
important that the reader examine this diagram carefully and check the correctness
of the circuit operation.
An application for pulse shifters is in the generation of enable signals (see section
3.11). In the case of i gure 3.18, the input is synchronous and its width is just one
clock period, being therefore simpler to generate than the generic case above (exercise
8.19).
8.11.10 Pulse Stretchers
This section presents another king of circuit that is a particular case of the triggered
circuits family introduced in section 8.11.8. It consists of “pulse stretchers,” which, as
the name indicates, take a pulse of shorter duration (often one clock period) and
stretch it to a longer length (in fact, one case was already seen in section 2.4 and
exercises 2.4 and 2.5). In i gure 8.29 an application for a pulse stretcher will be
presented.
The circuit ports are shown in i gure 8.27a, where
x
(short pulse) is the input
and
y
(longer pulse) is the output. The desired behavior is depicted in i gures 8.27b,c.
In i gure 8.27b the input is asynchronous and the output can be asynchronous (
y
goes to '1' as soon as
x
goes to '1') or synchronous (
y
changes only at clock edges). In
i gure 8.27c the input is synchronous and the output can again be asynchronous or
synchronous. As usual, cases with synchronous output can be implemented with
Figure 8.27
Pulse stretcher. (a) Circuit ports. Desired behavior for (b) asynchronous and (c) synchronous
input, both with asynchronous or synchronous output.
