Hardware Reference
In-Depth Information
8.11.9 Pulse Shifter
This section presents a circuit that is a particular case of the triggered circuits family
described above. It consists of a “pulse shifter,” which, as the name says, shifts a pulse
a certain number of time units. In other words, it makes a copy of a given pulse
T
shift
clock cycles later.
An example is presented in i gure 8.25. The circuit ports are shown in i gure 8.25a,
where
x
is the input (original pulse) and
y
is the output (shifted pulse). An illustrative
timing diagram is included if i gure 8.25b, which shows that
x
can be synchronous or
asynchronous. The time parameters are
T
pulse
= 3
T
clk
and
T
shift
= 8
T
clk
. Note, however,
that
T
pulse
is measured (inevitably) in
number of clock edges
rather than number of clock
periods (these values coincide when
x
is synchronous). The last (positive) clock edge
for which
x
= '0' was chosen as the reference for the shift; a different alternative would
be the i rst (positive) clock edge for which
x
= '1'.
A solution for this problem is presented in i gure 8.26a. Note the box above the
state
shift
, which says that
T
x
is a (registered) copy of
t
, enabled when
x
is high.
T
x
is
needed to keep track of the pulse's width, so the circuit can operate without any
a-priori information on the value of
T
pulse
.
Figure 8.25
Pulse shifter. (a) Circuit ports. (b) Desired behavior for both synchronous and asynchronous
input.
Figure 8.26
(a) FSM that implements the pulse shifter of i gure 8.25. (b) Corresponding timing diagram, for
T
pulse
= 3 and
T
shift
= 8 clock periods.