Hardware Reference
In-Depth Information
It is important to mention that the state transitions are always synchronous (gov-
erned by a clock signal). For example, if the machine is in the
idle
state and the condi-
tion
x
=
a
is true
at the moment when a (positive) clock edge occurs
, then the circuit moves
to state
char1
. A machine can operate either at the positive or negative clock edge, or
even at both clock edges if dual-edge l ip-l ops are employed. Unless specii ed other-
wise, it will be assumed (default) that it is a positive-edge machine.
Mealy-Type State Machines
An FSM is said to be of Mealy type when its input can affect the output directly. In
other words, the output now does not depend solely on the machine's state but also
depends on the input value. The resulting circuit is no longer truly synchronous
because the output might now change independently of the clock.
A Mealy-type solution for the same problem of i gure 1.3a is depicted in i gure 1.3c.
Because the output can now exhibit more than one value for the same state (because
the output also depends on the input value), the output values can no longer be written
inside the state circles. Note that they are indeed marked on the arrows, along with
the input (transition condition) values. Additionally, to simplify the notation, in the
Mealy machine the signal names are generally omitted (they are indicated separately,
as in the small rectangle of i gure 1.3c). In this example the Mealy parameters are
x
/
y
,
meaning “if
x
= value, then
y
= value”; for example,
a
/'0' means “if
x
=
a
, then
y
= '0'.”
The meaning of the state diagram of i gure 1.3c is as follows. If the circuit is in state
A and the input is
x
=
a
, the output is
y
= '0', and the next state (at the next positive
clock edge) will be B; otherwise, the output is still
y
= '0', but the next state will be A.
Likewise, if the machine is in state C and the input is
x
=
a
, then the output is
y
= '0',
and the next state will be B; otherwise, if the input is
x
=
c
, the output is
y
= '1', and
the next state will be A; else, the output is
y
= '0', but the next state will still be A. A
similar reasoning can easily be applied to state B. The direct dependence of the output
on the input can easily be observed in the state diagram; for example, note that in state
C the value of
y
varies with
x
, resulting in
y
= '1' when
x
=
c
or
y
= '0' otherwise.
Because modern designs are generally synchronous, the Moore option tends to be
preferred whenever the application permits.
Further details on Moore and Mealy constructions are seen in sections 1.7 and 1.8,
in which the conversion from one to the other is described.
1.4 Equivalent State Transition Diagram Representations
Unconditional and equivalent representations for the state transition diagram are
shown in i gure 1.4, where a 1-to-5 counter is used as an example. Two cases are con-
sidered. The case in i gure 1.4a has only clock and reset as inputs and as output has the
3-bit signal
outp
that encodes the counting. The case in i gure 1.4c has an additional
