Hardware Reference
In-Depth Information
The case in i gure 8.4d is also similar to that in i gure 8.4b, with state B again
untimed. However, note that there are values of
x
(“01” and “10”) that might cause
the machine to stay in state A even if
t
max
is reached. Because the timer is zeroed
after
t
max
occurs, our tentative strategy does not work here either. A possible solution
in this case is to stop the timer at
t
max
, zeroing it only when the machine changes
state.
Based on the analysis above and that in section 8.4, two timer control strategies
are proposed next.
8.5.2 Timer Control Strategy #1 (Generic)
A strategy that complies with all conditions described in section 8.4 and, consequently,
with all conditions in the examples of i gure 8.4, is summarized below.
For stopping the timer:
Stop the timer when it reaches the monitored value (or a pre-
dei ned value above that). Keep it so until the machine changes its state.
For zeroing the timer:
Zero the timer whenever the machine changes state.
To apply the timer-zeroing technique above, we can compare
pr_state
to
nx_state
.
If they are different, it means that the FSM will change its state at the next clock edge,
so a l ip-l op clearing command can be produced to zero the timer when such a transi-
tion occurs.
The advantages of this strategy are that it is generic, simple to understand, and
simple to implement. The construction of state transition diagrams using it is simple
and direct as well. Additionally, the timer does not need to be controlled in the
untimed states because it will run only up to a certain value and will stop anyway, so
power consumption is generally not a problem. Also, if one wants, a value greater
than
t
max
can be employed (see comments in section 8.3.2), which can simplify the
t
-to-
t
max
comparator (recall that this comparator can be large; for example, to produce
a 1 s delay from a 100 MHz clock, a 27-bit counter is needed); for instance, if
T
(=
t
max
+ 1) is a power of 2, only a single bit (the MSB) needs to be monitored.
Its main disadvantage is that the
pr_state
-to-
nx_state
comparator can be a large
circuit, because the number of bits in these two signals can be large, particularly when
the number of states is high and one-hot encoding is employed (sequential or gray
encoding is suggested when using strategy #1).
The following procedure is recommended: Use strategy #1, which is generic, to
draw the state transition diagram. After completing it, check whether it complies with
condition 1 or 2 described below for strategy #2. If it does, strategy #2 too can be used
to build the timer.
There are only few cases in which strategy #1 cannot be applied completely, but
the required adjustments are simple to handle. Such cases will be illustrated in sections
8.7 and 8.11.8.
