Hardware Reference
In-Depth Information
When using VHDL or SystemVerilog, one of the following codes can be used to
implement the timer using strategy #1. Note the use of t
t max , which can be a slightly
smaller comparator circuit than t
<
t max , but either one is i ne.
--Timer for strategy #1-------------------------
--VHDL------------------------------------------
process (clk, rst)
begin
if rst='1' then
t <= 0;
elsif rising_edge(clk) then
if pr_state /= nx_state then
t <= 0;
elsif t /= tmax then --see comment
t <= t + 1;
end if;
end if;
end process;
------------------------------------------------
--SystemVerilog---------------------------------
always_ff @(posedge clk, posedge rst)
if (rst) t <= 0;
else if (pr_state != nx_state) t <= 0;
else if (t != tmax) t <= t + 1; --see comment
------------------------------------------------
8.5.3 Timer Control Strategy #2 (Nongeneric)
This strategy is not generic because it cannot be employed in any timed machine. For
example, it only works properly for machines a and b of i gure 8.4. The procedure is
summarized below.
For stopping the timer: Do not stop the timer.
For zeroing the timer: Zero the timer after it reaches t max = T
1. In the untimed states,
adopt t max = 0 (timer stopped at zero).
This strategy can be applied in the following cases:
1) To any timed machine without conditional-timed transitions (i gure 8.4a, for
example).
2) To timed machines with conditional-timed transitions but only if no state has more
than one value for T , if no state can last longer than T clock periods, and if any transi-
tion that might last less than T clock cycles goes to an untimed state (i gure 8.4b, for
example).
The advantage of this strategy is that it avoids the pr_state -to- nx_state comparator,
which can be a large circuit.
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