Hardware Reference
In-Depth Information
Figure 8.4
Four timed machines. (a) With only conditional and timed transitions. (b) With conditional and
conditional-timed transitions but with state B untimed. (c) Same as b but with state B timed. (d)
Same as b but with conditional values (“01” and “10”) that might require the machine to remain
in state A longer than
T
clock periods.
'1' means
x
= '1' and
T
1. As usual, it is assumed that a regular
sequential counter running from
t
= 0 up to
t
=
T
−
1 means
t
=
T
−
−
1 is employed to build the timer.
8.5.1 Preliminary Analysis
A “tentative” strategy is assumed in this preliminary analysis, which consists of zeroing
the timer after it reaches the monitored value (
t
max
=
T
−
1), with
t
max
= 0 adopted in
the untimed states.
The machine in i gure 8.4a has only conditional and timed transitions, so the timer
always runs exactly up to
t
max
, after which the machine changes its state. Since it is
assumed here that the timer is always zeroed after
t
max
occurs, the timer will always
be cleared when the FSM enters a new state, causing it to work properly.
The machine in i gure 8.4b has a conditional-timed transition. If
x
= '0' occurs
before
t
=
t
max
, the machine moves from A to B with the timer at an unknown (
t
max
) value.
Consequently, the timer will not be zeroed here. However, because state B is untimed,
so
t
max
= 0, the timer will be zeroed at the end of the i rst clock period after entering
state B. As a result, the timer will be ready to operate properly even if state C is timed.
The case in i gure 8.4c is similar to that in i gure 8.4b, but state B is now timed.
Because the machine will enter state B with
t
<
t
max
, the timer will span in state B only
the number of clock cycles needed to complete state B's
t
max
. In summary, our tentative
timer control strategy is not appropriate for this machine.
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