Hardware Reference
In-Depth Information
results, so a i ve-bit counter is needed to build the timer (thus able to run from 0 up
to 31). The ranges of interest in this case are 0-to-24 in state S
1
and 0-to-7 in state S
2
.
8.4 Transition Types and Timer Usage
The state machine of i gure 8.3, which contains all four possible transition types, is
again used in the analysis that follows.
Transition AB is time independent, so the timer is not needed. Consequently, we
can let the timer run freely (for example, from 0 to 2
N
1, restarting then automati-
cally from 0), or let it run up to a certain value and then stop it, or simply keep it
stopped (at zero, for example). Keeping the timer stopped saves power but can
increase the complexity of the comparator. However, if the timer runs up to a certain
value and then stops (remaining so until the machine changes its state), the addi-
tional power consumption will generally be negligible. In case one decides to keep
the timer stopped at zero,
T
= 1 should be used (timer running from 0 to
t
max
=
T
−
−
1 = 0).
Transition BC is timed, so the timer is needed. The machine must stay in state B
during
exactly
T
clock periods, moving then to state C. Consequently, we can stop the
timer when the monitored value (
t
max
=
T
−
1) is reached or we can simply let it run
1, restarting then automatically from 0) because
the machine will change its state anyway after
t
=
t
max
occurs.
Transition CD is conditional-timed, so the timer is again needed. The machine must
move to state D at the i rst (positive) clock edge that i nds
x
= '0' after staying in state
C during
T
clock periods (so it will stay in C during
at least T
clock periods). In this
case we cannot let the timer run freely because then if
x
= '0' is not satisi ed when
the timer reaches the monitored value (
t
max
=
T
freely (for example, from 0 to 2
N
−
1) the condition
x
= '0' will only be
effective again when the timer passes through that value once more. A possible solu-
tion here is to stop the timer when the monitored value is reached (indeed, any value
−
≥
t
max
would do—see comments in section 8.3.2).
Finally, transition DA is unconditional, so the same comments made for transition
AB apply here.
In the next section, the possible timer usages described above will be considered
in order to develop systematic strategies for designing the timer.
8.5 Timer Control Strategies
We can now develop systematic strategies for controlling the timer. Figure 8.4 is used
to illustrate the discussions that follow. Note that all four machines are timed. The
timed states (states that need the timer) are represented with a darker shade of gray.
A simplii ed representation was employed for the transition conditions; for example,
