Hardware Reference
In-Depth Information
20
always_comb
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case (pr_state)
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idle: begin
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selA <= 1'bx;
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selB <= 1'bx;
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wrA <= 1'b0;
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wrB <= 1'b0;
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ALUop <= 0;
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if (dv) nx_state <= load;
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else nx_state <= idle;
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end
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load: begin
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selA <= 1'b1;
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selB <= 1'b1;
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wrA <= 1'b1;
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wrB <= 1'b1;
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ALUop <= 0;
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nx_state <= waitt;
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end
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waitt: begin
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selA <= 1'bx;
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selB <= 1'bx;
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wrA <= 1'b0;
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wrB <= 1'b0;
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ALUop <= 2;
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if (sign==1) nx_state <= writeA;
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else if (sign==2) nx_state <= writeB;
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else nx_state <= idle;
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end
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writeA: begin
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selA <= 1'b0;
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selB <= 1'bx;
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wrA <= 1'b1;
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wrB <= 1'b0;
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ALUop <= 2;
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nx_state <= waitt;
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end
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writeB: begin
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selA <= 1'bx;
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selB <= 1'b0;
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wrA <= 1'b0;
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wrB <= 1'b1;
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ALUop <= 3;
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nx_state <= waitt;
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end
65
endcase
66
67 endmodule
68 //----------------------------------------------------------------
7.8 Exercises
Exercise 7.1: Parity Detector
Solve exercise 6.1 using SystemVerilog instead of VHDL.
