Hardware Reference
In-Depth Information
7.7 Design of a Datapath Controller for a Greatest Common Divisor Calculator
This section presents a SystemVerilog-based design for the control unit introduced in
section 5.4.8, which controls a datapath to produce a greatest common divisor (GCD)
calculator. The Moore template of section 7.3 is employed to implement the FSM of
i gure 5.13e.
The i rst part of the code (
module header
) is in lines 1-6. The module's name is
control_unit_for_GCD
. Note that all ports are of type
logic
.
The second part of the code (
declarations
) is in lines 8-11. The enumerated type
state
is created in it to represent the machine's present and next states.
The third and i nal part of the code (
statements
) is in lines 13-67. It contains two
always
blocks, described next.
The i rst
always
block (lines 15-17) is an
always_ff
, which implements the
machine's state register. This is a standard code, similar to the template.
The second
always
block (lines 20-65) is an
always_comb
, which implements the
entire combinational logic section. It is just a list of all states, each containing the
output values and the next state. Note that in each state the output values are unique
because in a Moore machine the outputs depend only on the state in which the
machine is.
Finally, and very importantly, observe the correct use of registers and the complete-
ness of the code, as described in comment 8 of section 7.3. Observe in particular the
following: 1) all states are included; 2) the list of outputs is exactly the same in all
states, and the corresponding values are always included; 3) the conditional specii ca-
tions for
nx_state
are always i nalized with an
else
statement, so no condition is left
unchecked.
1 //Module header:--------------------------------------------------
2 module control_unit_for_GCD (
3
input logic dv, clk, rst,
4
input logic [1:0] sign,
5
output logic selA, selB, wrA, wrB,
6
output logic [1:0] ALUop);
7
8 //Declarations:---------------------------------------------------
9
//FSM states type:
10
typedef enum logic [2:0] {idle, load, waitt, writeA, writeB} state;
11
state pr_state, nx_state;
12
13 //Statements:-----------------------------------------------------
14
//FSM state register:
15
always_ff @(posedge clk, posedge rst)
16
if (rst) pr_state <= idle;
17
else pr_state <= nx_state;
18
19
//FSM combinational logic:
