SystemVerilog Design of Regular (Category 1) State Machines - Finite State Machines in Hardware - page 142

Exercise 7.2: One-Shot Circuits
Solve exercise 6.2 using SystemVerilog instead of VHDL.
Exercise 7.3: Manchester Encoder
Solve exercise 6.3 using SystemVerilog instead of VHDL.
Exercise 7.4: Differential Manchester Encoder
Solve exercise 6.4 using SystemVerilog instead of VHDL.
Exercise 7.5: String Detector
Solve exercise 6.5 using SystemVerilog instead of VHDL.
Exercise 7.6: Generic String Detector
Solve exercise 6.6 using SystemVerilog instead of VHDL.
Exercise 7.7: Keypad Encoder
Solve exercise 6.7 using SystemVerilog instead of VHDL.
Exercise 7.8: Datapath Controller for a Largest-Value Detector
Solve exercise 6.8 using SystemVerilog instead of VHDL.