Hardware Reference
In-Depth Information
50
else nx_state <= open2;
51
end
52
closing1: begin
53
ctr <= 2'b11;
54
if (sen2) nx_state <= closed1;
55
else if (~remt) nx_state <= closing2;
56
else nx_state <= closing1;
57
end
58
closing2: begin
59
ctr <= 2'b11;
60
if (remt | sen2) nx_state <= closed1;
61
else nx_state <= closing2;
62
end
63
endcase
64
65 endmodule
66 //-------------------------------------------------------
The number of l ip-l ops inferred by the compiler after synthesizing the code above
was three for sequential or Gray encoding, four for Johnson, and eight for one-hot,
matching the predictions made in section 5.4.5.
Simulation results are depicted in i gure 7.4. The encoding chosen for the states
was
sequential
(section 3.7). The states are enumerated from 0 to 7 (there are eight
states) in the order in which they were declared in lines 8-9. Be aware, however, that
some compilers reserve the value zero for the reset state; because the reset (initial)
state in the present example is
closed1
(see line 15), which is the i rst state in the
declaration list, that is not a concern here.
In this simulation the sequence
closed1—closed2—opening1—opening2—open1—
open2—closing1—closed1
(see state names in the lower part of i gure 7.4) was tested.
Note that pulses of various widths were used to illustrate the fact that their width has
no effect beyond the i rst positive clock edge.
Figure 7.4
Simulation results from the SystemVerilog code for the garage door controller of i gure 5.9c.
