Hardware Reference
In-Depth Information
following: 1) all states are included; 2) the list of outputs (only
ctr
in this case) is
exactly the same in all states, and the corresponding values are always included; 3)
the specii cations for
nx_state
are always i nalized with an
else
statement, so no condi-
tion is left unchecked.
1 //Module header:-----------------------------------------
2 module garage_door_controller (
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input logic remt, sen1, sen2, clk, rst,
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output logic [1:0] ctr);
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6 //Declarations:------------------------------------------
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//FSM states type:
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typedef enum logic [2:0] {closed1, closed2, opening1,
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opening2, open1, open2, closing1, closing2} state;
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state pr_state, nx_state;
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12 //Statements:--------------------------------------------
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//FSM state register:
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always_ff @(posedge clk, posedge rst)
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if (rst) pr_state <= closed1;
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else pr_state <= nx_state;
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//FSM combinational logic:
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always_comb
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case (pr_state)
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closed1: begin
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ctr <= 2'b0x;
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if (~remt) nx_state <= closed2;
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else nx_state <= closed1;
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end
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closed2: begin
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ctr <= 2'b0x;
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if (remt) nx_state <= opening1;
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else nx_state <= closed2;
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end
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opening1: begin
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ctr <= 2'b10;
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if (sen1) nx_state <= open1;
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else if (~remt) nx_state <= opening2;
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else nx_state <= opening1;
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end
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opening2: begin
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ctr <= 2'b10;
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if (remt | sen1) nx_state <= open1;
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else nx_state <= opening2;
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end
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open1: begin
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ctr <= 2'b0x;
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if (~remt) nx_state <= open2;
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else nx_state <= open1;
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end
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open2: begin
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ctr <= 2'b0x;
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if (remt) nx_state <= closing1;
